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MH88437-P
Data Access Arrangement
Features
* * * * * * * * * * * * * * * * * FAX and Modem interface (V.34/V.34+) Designed to work at data rates up to 56kbits External programmable line and network balance impedances Programmable DC termination characteristics IEC950 recognised component Transformerless 2-4 Wire conversion Integral Loop Switch Dial Pulse and DTMF operation Accommodates parallel phone detection Line state detection outputs: -loop current/ringing voltage/line voltage +5V operation, low on-hook power (25mW) Full duplex voice and data transmission On-Hook reception from the line Meets French current limit requirements Conforms to German dial pulse standards Approvable to UL 1950 Industrial Temperature Range Available
DS5060
ISSUE 5
November 2001
Package Information MH88437AD-P 28 Pin DIL Package MH88437AS-P 28 Pin SM Package MH88437AS-PR28 Pin SM Package (Tape & Reel) 0C to +70C
Description
The Zarlink MH88437 Data Access Arrangement (D.A.A.) provides a complete interface between audio or data transmission equipment and a telephone line. All functions are integrated into a single thick film hybrid module which provides high voltage isolation, very high reliability and optimum circuit design, needing a minimum of external components. The impedance and network balance are externally programmable, as are the DC termination characteristics, making the device suitable for most countries worldwide.
Applications
Interface to Central Office or PABX line for: * FAX/Modem * Electronic Point of Sale * Security System * Telemetry * Set Top Boxes
Isolation Barrier VCC VBIAS AGND CL LC VR+ VRNB1 NB2 THL cancellation and line impedance matching circuit VX ZA RV LCD LOOP RS
OptoIsolation TIP RING Input Buffer & Line Termination
Logic Input Buffer
Isolation
Analog Buffer
VLOOP1 VLOOP2
Isolation
Analog Buffer Ring & Loop Buffer
Isolation
Network Connections
User Connections
Figure 1 - Functional Block Diagram
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MH88437-P
NB1 NB2 VR+ VRVX LC ZA AGND VCC VBIAS LOOP IC RS IC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TIP RING C1 VLOOP1 VLOOP2 C2 SC SC IC NP NP CL RV LCD
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12, 14 13 15 16 17 18 19
2
Name NB1 NB2 VR+ VRVX LC ZA AGND VCC VBIAS LOOP IC RS LCD RV CL NP NP
Description Network Balance 1. External passive components must be connected between this pin and NB2. Network Balance 2. External passive components must be connected between this pin and NB1. Differential Receive (Input). Analog input from modem/fax chip set. Differential Receive (Input). Analog input from modem/fax chip set. Transmit (Output). Ground referenced (AGND) output to modem/fax chip set, biased at +2.0V. Loop Control (Input). A logic 1 applied to this pin activates internal circuitry which provides a DC termination across Tip and Ring. This pin is also used for dial pulse application. Line Impedance. Connect impedance matching components from this pin to Ground (AGND). Analog Ground. 4-Wire 0V reference connect to mains earth (ground). Positive Supply Voltage. +5V. Internal Reference Voltage. +2.0V reference voltage. This pin should be decoupled externally to AGND, typically with a 10F 6.3V capacitor. Loop (Output). The output voltage on this pin is proportional to the line voltage across Tip Ring, scaled down by a factor of 50. Internal Connection. No connection should be made to this pin externally. Ringing Sensitivity. Connecting a link or resistor between this pin and LOOP (pin 11) will vary the ringing detection sensitivity of the module. Loop Condition Detect (Output). Indicates the status of loop current. Ringing Voltage Detect (Output). The RV output indicates the presence of a ringing voltage applied across the Tip and Ring leads. Current Limit. A logic 0 applied to this pin activates internal circuitry which limits the loop current. No Pin. Isolation Barrier, fitted, no pin fitted in this position. No Pin. Isolation barrier, no pin fitted in this position
MH88437-P
Pin Description (continued)
Pin # 20 21,22 24 25 27 28 26,23 Name IC SC VLOOP2 VLOOP1 RING TIP C1, C2 Description Internal Connection. No connection should be made to this pin externally. Short Circuit. These two pins should be connected to each other via a 0 link. Loop Voltage Control Node 2. Used to set DC termination characteristics. Loop Voltage Control Node 1. Used to set DC termination characteristics. Ring Lead. Connects to the "Ring" lead of the telephone line. Tip Lead. Connects to the "Tip" lead of the telephone line. Cap. Fit a 22nF Cap between these two pins. CTR21 is generally accepted within Europe, and this route should be selected for those countries. This should be attempted with the consultation of a local approvals house. Approval specifications are regularly changing and the relevant specification should always be consulted before commencing design.
Functional Description
The device is a Data Access Arrangement (D.A.A.). It is used to correctly terminate a 2-Wire telephone line. It provides a signalling link and a 2-4 Wire line interface between an analog loop and subscriber data transmission equipment, such as Modems, Facsimiles (Fax's), Remote Meters, Electronic Point of Sale equipment and Set Top Boxes.
Line Termination Isolation Barrier
The device provides an isolation barrier capable of meeting the supplementary barrier requirements of the international standard IEC 950 and the national variants of this scheme such as EN 60950 for European applications and UL 1950 for North American applications. When Loop Control (LC) is at a logic 1, a line termination is applied across Tip and Ring. The device can be considered off-hook and DC loop current will flow. The line termination consists of both a DC line termination and an AC input impedance. It is used to terminate an incoming call, seize the line for an outgoing call, or if it is applied and disconnected at the required rate, can be used to generate dial pulses. The DC termination resembles approximately 300 resistance, which is loop current dependent. Furthermore, it can be programmed to meet different national requirements. For normal operation VLOOP3 should be open circuit and a resistor (R2) should be fitted between VLOOP1 and VLOOP2, as shown in Figure 4. The approval specification will give a DC mask characteristic that the equipment will need to comply to. The DC mask specifies the amount of current the DAA can sink for a given voltage across tip and ring. Graph 1 shows how the voltage across tip and ring varies with different resistors (R2) for a given loop current.
External Protection Circuit
An External Protection Circuit assists in preventing damage to the device and the subscriber equipment, due to over-voltage conditions. See Application Note MSAN-154 for recommendations.
Suitable Markets
The MH88437 has features such as programmable line and network balance impedance, programmable DC termination and a supplementary isolation barrier. For countries that do not need to meet the French and German requirements there is a pin for pin compatible device the MH88435. There are, however, a small number of countries with a 100M leakage requirement that this device does not meet. These are Belgium, Greece, Italy, Luxembourg, Spain and Poland.
Network Balance
The network balance impedance of the device can be programmed by adding external components By applying a logic 0 to Pin 17, CL, the loop current will
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MH88437-P
40
35
30
Iloop=15mA 25
V(t-r)
Iloop=20mA Iloop=26mA
20
15
10
5
0 50 150 250 350 450 550 650 750 850 950
R2(kOhms) Figure 3 - DC Programming Capability be limited to below 60mA as required in France and the European TBR21 specification. For all other countries where current limiting is not required, CL should be set to 1. The AC input impedance should be set by the user to match the line impedance. Zext = [(10 x R1)-1k3]+[(10 x R2)//(C1/10)] e.g. If the required input impedance = 220 + (820/ /115nF), the external network to be connected to ZA will be: ZA = 900 + (8k2//12nF) Where the input impedance (Z) = 600R the equation can be simplified to: ZA = (10 x Z) - 1k3 ZA = 4k7 Note: A table of commonly used impedances can be found in the DAA Application's document MSAN-154. Where Zext = external network connected between ZA and AGND and Zint = 1.3k (internal resistance) between NB1 and NB2. For countries where the balance impedance matches the line impedance, a 16k resistor should be added between NB1 and NB2.
Input Impedance
The MH88437 has a programmable input impedance set by fitting external components between the ZA pin and AGND. For complex impedances the configuration shown in Figure 4 (below) is most commonly found.
R1
R2
C1
Figure 4 - Complex Impedances To find the external programming components for configuration 4, the following formula should be used:
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MH88437-P
Ringing Voltage Detection
The sensitivity of the ringing voltage detection circuitry can be adjusted by applying an external resistor (R7, Figure 5) between the RS and LOOP pins. With a short circuit, the threshold sensitivity is ~10Vrms, therefore R7 = 30k x (Desired threshold voltage - 10Vrms). Example: 300k gives ~20Vrms and 600k gives ~30Vrms. An AC ringing voltage across Tip and Ring will cause RV to output TTL pulses at the ringing frequency, with an envelope determined by the ringing cadence.
2-4 Wire Conversion
The device converts the balanced 2-Wire input, presented by the line at Tip and Ring, to a ground referenced signal at VX, biased at 2.0V. This simplifies the interface to a modem chip set. Conversely, the device converts the differential signal input at VR+ and VR- to a balanced 2-Wire signal at Tip and Ring. The device can also be used in a single ended mode at the receive input, by leaving VR+ open circuit and connecting the input signal to VR- only. Both inputs are biased at 2.0V. During full duplex transmission, the signal at Tip and Ring consists of both the signal from the device to the line and the signal from the line to the device. The signal input at VR+ and VR- being sent to the line, must not appear at the output VX. In order to prevent this, the device has an internal cancellation circuit, the measure of this attenuation is Transhybrid Loss (THL). The MH88437 has the ability to transmit analog signals from Tip and Ring through to VX when onhook. This can be used when receiving caller line identification information.
Parallel Phone and Dummy Ringer
An external parallel phone or dummy ringer circuit can be connected across Tip and Ring as shown in Figure 5. A Dummy Ringer is an AC load which represents a telephone's mechanical ringer. In normal circumstances when a telephone is OnHook and connected to the PSTN, its AC (Ringer) load is permanently presented to the network. This condition is used by many PTT's to test line continuity, by placing a small AC current onto the line and measuring the voltage across tip (A) and ring (B). Today's telecom equipment may not have an AC load present across tip and ring (e.g. modems), therefore any testing carried out by the PTT will see an open circuit across tip and ring. In this instance the PTT assumes that the line continuity has been damaged. To overcome this problem many PTT's specify that a "Dummy Ringer" is presented to the network at all times. Ideally its impedance should be low in the audio band and high at the ringing frequencies (e.g. 25Hz). Note that the requirement for the "Dummy Ringer" is country specific. Parallel phone detection is used mostly in set-top box applications. This is when a modem call will need to be disconnected from the central office by the equipment when the parallel phone is in the offhook state. This is to allow the subscriber to make emergency calls. To detect this state, additional circuitry will be required. Refer to Application Note MSAN-154.
Transmit Gain
The Transmit Gain of the MH88437 is the gain from the differential signal across Tip and Ring to the ground referenced signal at VX. The internal Transmit Gain of the device is fixed as shown in the AC Electrical Characteristics table. For the correct gain, the Input Impedance of the MH88437, must match the specified line impedance. By adding an external potential divider to VX, it is possible to reduce the overall gain in the application. The output impedance of VX is approximately 10 and the minimum resistance from VX to ground should be 2k. Example: If R3 = R4 = 2k, in Figure 5, the overall gain would reduce by 6.0dB.
Receive Gain
The Receive Gain of the MH88437 is the gain from the differential signal at VR+ and VR- to the differential signal across Tip and Ring. The internal Receive Gain of the device is fixed as shown in the AC Electrical Characteristics table. For the correct
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MH88437-P
gain, the Input Impedance of the MH88437 must match the specified line impedance. With an internal series input resistance of 47k at the VR+ and VR- pins, external series resistors can be used to reduce the overall gain. Overall Receive (47k+R5)). Gain = 0dB+20log (47k/
For differential applications R6 must be equal to R5 in Figure 5. Example: If R5 = R6 = 47k in Figure 3, the overall gain would reduce by 6.0dB.
Supervisory Features
The device is capable of monitoring the line conditions across Tip and Ring, this is shown in Figure 5. The Loop Condition Detect pin (LCD), indicates the status of the line. The LCD output is at logic 1 when loop current flows, indicating that the MH88437 is in an off hook state. LCD will also go high if a parallel phone goes off-hook. Therefore, line conditions can be determined with the LC and the LCD pins. The LOOP pin output voltage VLOOP is proportional to the line voltage across Tip and Ring scaled down by a factor of 50 and offset by 2.0V(t-r). With the aid of a simple external detector the LC, LCD and LOOP pins can be used to generate the signals necessary for parallel phone operation, e.g. with a Set Top Box. See MSAN-154 for further details. When the device is generating dial pulses, the LCD pin outputs TTL pulses at the same rate. The LCD output will also pulse if a parallel phone is used to dial and when ringing voltage is present at Tip and Ring.
Mechanical Data
See Figures 12, 13 and 14 for details of the mechanical specification.
6
MH88437-P
+5V
C2
+
9 25 24 VLOOP1 VLOOP2 VCC
R2 21 22 13 11 LOOP RS
R7
C8 28 L2 R1
R4 5 4 3 16 15 6 1 2 CL ZB R3 R5 R6 C4 C5 C6 Analog Output Analog Input Analog Input Ringing Voltage Detect Output Loop Current Detect Output Loop Control Input
TIP
TIP
VX VRMH88437 VR+ RV
D1 D2 C1 L1 RING 23 RING AGND VBIAS 10 26 8 C9 C3 + ZA 7 LCD LC NB1 NB2
C7
Zext Notes: 1) R1 & C1: Dummy Ringer, country specific typically 0.39F, 250V & 3k 2) R2: DC Mask Resistor 82k typical 3) R3 & R4: Transmit Gain Resistors 2k2 4) R5 = R6: Receive Gain Resistors typically 100k 5) ZB: Network Balance Impedance 6) C2 & C3 = 10F 6V 7) C7 & C8 = 39nF for 12kHz filter and 22nF for 16KHz filter. These can be left off if meter pulse filtering not required. 8) Zext: External Impedance 9) D1 Zener Diode 9V1 (x2) 10) L1, L2 = 4.7mH RDC<10. These can be left off if meter pulse filtering not required. 11) C4, C5 & C6 = 1F coupling capacitors 12) R7 = 620k (30V RMS ringing sensitivity) 13) D2 = Teccor P2703 Protection 14) C9 = 22nF
= Ground (Earth)
Figure 5 - Typical Application Circuit
7
MH88437-P
.
Absolute Maximum Ratings* - All voltages are with respect to AGND unless otherwise specified.
Parameter 1 2 3 4 5 6 7 DC Supply Voltage Storage Temperature DC Loop Voltage Transient loop voltage Ringing Voltage Loop Current Ring Trip Current Sym VCC TS VTR VTR VR ILOOP ITRIP Min -0.3 -55 -110 Max 6 +125 +110 300 150 60 90 180 Units V C V V Vrms mA mA mArms 1ms On hook VBAT = -56V CL=0 VTIP-RING 40V CL=1 250ms 10% duty cycle or 500ms single shot Comments
*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions
Parameter 1 2 3 DC Supply Voltages Operating Temperatures Industrial Temperature Ringing Voltage Sym VCC TOP VR Min 4.75 0 -40 Typ 5.0 25 75 Max 5.25 70 +85 90 Units
V
Test Conditions
C Vrms VBat = -48V
Typical figures are at 25C with nominal +5V supply and are for design aid only
Loop Electrical Characteristics
Characteristics 1 Ringing Voltage No Detect Detect 2 3 4 Ringing Frequency Operating Loop Current Off-Hook DC Voltage 6.0 6.0 7.8 5 6 7 8 Leakage Current (Tip or Ring to AGND) Leakage Current on-hook (Tip to Ring) Dial Pulse Detection ON OFF 0 0 5 9 18 +1 +1 10 7 10 20 +2 +2 16 V V V A mA ms ms V Sym VR 7 14 15 15 68 60 80 Vrms Vrms Hz mA mA CL=0 VTIP-RING 40V CL=1 (see Note 1) Externally Adjustable ILOOP=15mA) ILOOP=20mA) (Note 3) ILOOP=26mA) where R2 = 110k 100V DC (see Note 2) 1000V AC VBAT (= -50V) VBAT (= -100V) Dial pulse delay Voltage across tip and ring Min Typ Max Units Test Conditions Externally Adjustable
Loop Condition Detect Threshold Off-Hook
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal + 5V supplies and are for design aid only. Note 1: Low Loop current operation depends on value of resistor connected between VLoop 1 and VLoop 2. Note 2: This is equivalent to 10M leakage Tip/Ring to Ground. Note 3. Refer to EIA/TIA 464 Section 4.1.1.4.4 8
MH88437-P
DC Electrical Characteristics
Characteristics 1 2 3 RV, LCD LC Supply Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current DC common mode Sym ICC VOL VOH VIL VIH IIL IIH VCM 2.4 0.8 2.0 0 350 0 2 60 400 VCC Min Typ 5 0.4 Max Units mA V V V V A A VDC Test Conditions VDD (= 5.0V, On-hook) IOL = 4mA IOH = 0.4mA
VIL = 0.0V VIH = 5.0V Use coupling caps for higher voltages and single ended
4
VR+ VR-
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal + 5V supplies and are for design aid only.
AC Electrical Characteristics
Characteristics 1 Input Impedance VRVR+ 2 3 4 5 Output Impedance at VX Receive Gain (VR to 2-Wire) Frequency Response Gain (relative to Gain @ 1kHz) Signal Output Overload Level at 2-Wire at VX Signal/Noise & Distortion at 2-Wire at VX Power Supply Rejection Ratio at 2-Wire at VX Transhybrid Loss 2-Wire Input Impedance Return Loss at 2-Wire (Reference 600) SINAD 70 70 PSRR 25 25 THL Zin RL 14 20 18 24 24 24 dB dB dB 16 40 40 25 Note 3 dB dB dB dB dB -1 -0.5 10 0 0 1 0.5 Sym Min Typ 47k 94k Max Units Test Conditions
dB
dB
Test circuit (Figure 8) Input 0.5V at 1kHz
ILOOP = 15-60mA
300Hz to 3400 Hz THD < 5% @ 1kHz ILOOP = 25-60mA VCC = 5V Input 0.5V at 1kHz
0 0
dBm dBm
6
ILOOP = 25-60mA
300-3400Hz Ripple 0.1Vrms 1kHz on VDD Test circuit (Figure 8) 300-3400Hz at VR @ 1kHz Test circuit(Figure 9) 200-500Hz 500-2500Hz 2500-3400Hz
7
8 9 10
9
MH88437-P
AC Electrical Characteristics (continued)
Characteristics 11 Longitudinal to Metallic Balance Sym Nc 46 46 Metallic to Longitudinal Balance 60 40 12 Idle Channel Noise at 2-Wire at VX at 2-Wire at VX 13 Transmit Gain (2-Wire to VX) Off-Hook On-Hook 14 15 Frequency Response Gain (relative to Gain @ 1kHz) Intermodulation Distortion products at VX and 2W IMD -0.5 -0.5 -1 15 15 -65 -65 0 0 0 0 75 0.5 0.5 20 20 dBrnC dBrnC dBm dBm dB dB dB dB dB Cmess filter 300-3400Hz filter Test circuit (Figure 7) Input 0.5V @ 1kHz LC = 0V 300Hz 3400Hz ILOOP = 25-60mA F1 = 1kHz at -6dBm F2 = 800Hz at -6dBm Total signal power = -3dBm ILOOP = 25-60mA F1 = 1kHz at -6dBm F2 = 800Hz at -6dBm Total signal power = -3dBm Test circuit (Figure 10) 1-100Hz Note 4 Test circuit (Figure 10) 1-100Hz Note 4 dB dB 58 53 dB dB Min Typ Max Units Test Conditions Test circuit (Figure 10) 300-1000Hz 1000-3400Hz Test circuit (Figure 11) 200-1000Hz 1000-4000Hz
+1
16
Distortion at VX due to near end echo (300Hz - 3400Hz bandwidth)
75
dB
17 18
Common Mode Rejection at VX Common Mode overload
CMR CML
50 100V
dB Vpk-pk
Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal + 5V supplies and are for design aid only.
10
MH88437-P
11 LOOP 3 VR+ 4 5 21 22 22nF 82K VR-
13 RS
15 LCD 28 TIP NB1 1 16K NB2 2 ILOOP
DUT VX VLOOP5
VLOOP4 23 C2 26 C1 24 VLOOP2 25
RING
27
1K 5V
10 VBIAS VLOOP1 + 10uF LC RV AGND VCC ZA 9 7 6 16 8 4.7K
= Ground (Earth)
5V
Figure 6 - Test Circuit 1
-V 10H 500 100uF I=20mA +
11 3 4 5 21 22 LOOP VR+ VR-
13 RS
15 LCD 28 TIP NB1 1 16K NB2 2
DUT VX VLOOP5 Vs Impedance = Zin 100uF + 10H 500
22nF
VLOOP4 23 C2 26 C1 82K 24 VLOOP2 25
RING
27
1K 5V
10 VBIAS VLOOP1 + 10uF LC RV AGND VCC ZA 7 9 6 16 8 4.7K
5V Gain = 20 * Log (VX / Vs)
= Ground (Earth)
Figure 7 - Test Circuit 2
11
MH88437-P
-V 10H 500 11 LOOP 3 VR+ Vs 4 5 21 VRDUT VX VLOOP5 NB2 2 16K Zin 13 RS 15 LCD 28 TIP NB1 1 I=20mA 100uF +
22nF 82K
22 VLOOP4 23 C2 26 C1 24 VLOOP2 25
RING
27
100uF + 10H 500
1K 5V
10 VBIAS VLOOP1 10uF LC RV AGND VCC ZA + 9 6 16 8 7 4.7K
5V Gain = 20 * Log (V(Zin) / Vs)
= Ground (Earth)
Figure 8 - Test Circuit 3
-V 10H 500 11 LOOP 3 VR+ 4 5 21 VRDUT VX VLOOP5 NB2 2 300 100uF RING 27 10H 500 + 16K 13 RS 15 LCD 28 TIP NB1 1 V1 300 Vs = 0.5V I=20mA 100uF + Zin
22nF 82K
22 VLOOP4 23 C2 26 C1 24 25 VLOOP2
1K 5V
10 VBIAS VLOOP1 10uF LC RV AGND VCC ZA + 9 6 16 8 7 4.7K
5V Return Loss = 20 * Log (V1 / Vs)
= Ground (Earth) Figure 9 - Test Circuit 4
12
MH88437-P
-V 10H 500 11 3 4 5 21 LOOP VR+ VRDUT VX VLOOP5 NB2 2 16K V1 300 RING 27 100uF + 10H 500 Vs = 0.5V 13 RS 15 LCD 28 TIP NB1 1 300 I=20mA 100uF +
22nF 82K
22 VLOOP4 23 C2 26 C1 24 VLOOP2 25
1K 5V
10 VBIAS VLOOP1 + 10uF LC RV AGND VCC ZA 9 7 6 16 8 4.7K
5V Long. to Met. Balance = 20 * Log (V1 / Vs) CMR = 20 * Log (VX / Vs)
= Ground (Earth)
Figure 10 - Test Circuit 5
-V 10H 500 11 3 4 5 LOOP VR+ VRDUT VX NB2 2 300 100uF RING 27 + 10H 500 VBIAS 10 + 10uF 510 V1 16K Vs 13 RS 15 LCD 28 TIP NB1 1 300 I=20mA 100uF +
21 VLOOP5 22 VLOOP4 22nF 82K 23 C2 26 C1 24 VLOOP2 25 VLOOP1
1K 5V
LC RV AGND VCC ZA 9 7 6 16 8 4.7K
5V Met. to Long. Balance = 20 * Log (V1 / Vs)
= Ground (Earth) Figure 11 - Test Circuit 6
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MH88437-P
0.162 Max (4.12 Max) 0.27 Max (6.9 Max) 0.08 Typ (2 Typ) 1.00 Typ * (25.4 Typ) 1.05 Max (26.7 Max) * 0.100+0.010 (2.54+0.25) 0.020 + 0.005 (0.5 + 0.13) 0.063 Max (1.6 Max) 0.260+0.015 (6.6+0.38)
* 0.05 Typ (1.27 Typ) * 0.300+0.010 (7.62+0.25)
Notes: 1) Not to scale 2) Dimensions in inches. (Dimensions in millimetres) 3) Pin tolerances are non-accumulative. 4) Recommended soldering conditions: Wave Soldering - Max temp at pins 260C for 10 secs. * Dimensions to centre of pin.
1
1.42 Max (36.1 Max)
Figure 12 - Mechanical Data for 28 Pin DIL Hybrid
0.162 Max (4.11 Max) 0.265 Max (6.73 Max) 0.063 Max (1.6 Max) 0.99 Typ (25.15 Typ) 0.9 + 0.015 (2.3 + 0.38) * 0.100+0.010 (2.54+0.25) 0.020 + 0.005 (0.5 + 0.13) *0.300+0.010 (7.62+0.25) * 0.05 Typ (1.27 Typ) 0.060 Typ (1.52 Typ)
Notes: 1) Not to scale 2) Dimensions in inches. (Dimensions in millimetres) 3) Pin tolerances are non-accumulative. 4) Recommended soldering conditions: Max reflow temp: 220C for 10 secs. * Dimensions to centre of pin. 1.42 Max (36.1 Max) 1.15 Max (29.2 Max) 1
Figure 13 - Mechanical Data for 28 Pin Surface Mount Hybrid
14
MH88437-P
0.10 (2.54)
* 0.26 (6.60)
0.10 (2.54)
0.97 (24.64) 0.04 (1.02)
Notes: 1) Not to scale 2) Dimensions in inches. (Dimensions in millimetres) 3) All dimensions are Typical except where marked with an. This gap is associated with the isolation barrier.
0.06 (1.52)
Figure 14 - Recommended Footprint for 28 Pin Surface Mount Hybrid
15
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